Interface Control Document
ARINC 818 implementations are compatible only when they share an interface control document (ICD). Therefore, implementations must always be associated with ICDs. Among the basic features set out by the ICD are:
- video resolution;
- scan type;
- frame rate;
- pixel format.
Characteristics for more complex systems are also covered.
ADVB frame structure
Idle words: Idle ordered sets are transmitted between ADVB frames. Typically, a minimum of six idle ordered sets between each Fibre Channel frame is needed. When transmitting, the number of idle ordered sets between ADVB frames can be varied to adjust the video frame time (to adjust the horizontal blanking).
Start of frame: ARINC 818 is independent of class of service. Currently, Class 1 and Class 3 implementations exist.
Data payloads: The first frame of an ADVB container data sequence includes the container header and Object 0 ancillary data as its data payload. Subsequent frames of the container sequence include the Object 2 video pixel data. Each is limited to 2112 bytes, which may require a single line of video to be broken into multiple ADVB frames. In the XGA example, each of the 1024 RGB pixels in a line requires three bytes (3072 bytes per line), so a video line must be divided between two 2112-byte ADVB frames.
Cyclic Redundancy Check (CRC): After a video frame has been transmitted, a 4-byte CRC for error checking follows. It uses the following 32-bit polynomial:
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
End of frame: All frames except the last frame of an ADVB container data transfer sequence use the End of Frame Normal (EOFn) ordered set, beginning RD Negative or RD Positive.
The last frame of an FC-AV container data transfer sequence uses the End of Frame Terminate (EOFt) ordered set, beginning RD Negative or RD Positive.
Since the adoption of ARINC 818 more than a decade ago, custom implementations have led to a revised standard capable of such things as switching, data-only return paths (for control of sensor pods, for example), and regions of interest frames rates higher than the rest of the frame. Higher ARINC 818 link rates, currently up to 28.05 gigabits per second, are already in place to take advantage of faster FPGAs of tomorrow.